In this work we describe how to implement the Advanced Encryption Standard (AES) for a bit-serial fully pipelined architecture. This is possible through a requirements analysis and extension of the architecture. For the AES design, we rely on a high level synthesis tool to automatically generate the AES algorithm's elements. In addition to the implementation of the AES cipher, we describe a low- level space optimization approach to reduce the hardware utilization of our AES design. This involves a register transfer level analysis of the architecture's operators. The resulting correctly operating AES implementation was shrunk by about 25% through our optimization.

Данное издание не является оригинальным. Книга печатается по технологии принт-он-деманд после получения заказа.