Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. In personal computer microprocessor architecture, a back side bus (BSB), or backside bus, is a computer bus used to connect the CPU to CPU cache memory, usually L2. If a design utilizes it along with a front-side bus (FSB), it is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB) architecture. BSB is an improvement over the older practice of accessing the cache over the front side bus (FSB), because FSB is typically a severe bottleneck in modern systems. In addition, due to its dedicated nature, the back side bus can be optimized or customized for communication with cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose FSB. Furthermore, since a BSB operates over a shorter distance, it can typically operate at higher clock speeds, increasing the computer's overall performance.

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