High Quality Content by WIKIPEDIA articles! Column Address Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins. In general, the lower the CAS latency, the better. In asynchronous DRAM, the interval is specified in nanoseconds. In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of an arbitrary time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.

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