Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. Cycle stealing is used to describe the "stealing" of a single CPU cycle, for example, to allow a DMA controller to perform a DMA operation. This is opposed to block operation where a DMA controller would request a bus, hold it for a complete transaction (typically 16-32 bytes but could last much longer) before releasing to a CPU. Cycle stealing generally occurs when the entire DMA transfer of data is finished, the DMA controller interrupts the CPU. This term is less common in modern computer architecture (say above 66-100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations.

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