The continuous quest for higher circuit performance has pushed clock frequencies deep into the gigahertz frequencies range, reducing the period of the clock signal well below a nanosecond. The resulting constraints demonstrate the requirement for tight timing control of the arrival times of the clock signal at the many clocked elements throughout an integrated circuit. In this book, a design methodology for enhancing the tolerance of a circuit to the uncertainty of the clock signal delay is presented. This methodology either relaxes the timing constraints at the most critical data paths, or reduces the delay uncertainty among the clock signals that synchronize these paths. Power tradeoffs of the proposed design techniques are investigated and physical layout information is incorporated to synthesize the clock tree layout based on a set of benchmark circuits. This book provides the reader with information on those effects that introduce delay uncertainty and with the tools to successfully design high performance synchronous circuits. The original research presented in this book has been awarded with the Outstanding Dissertation Award by the European Design Automation Association.

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