Implementations of theoretically secure cryptographic algorithms can be broken by side-channel attacks. In particular, block ciphers have turned out to be very susceptible to differential power-analysis (DPA) attacks. Various methods to prevent these attacks have been proposed so far. This book is about countermeasures against DPA attacks, which can be easily implemented in a standard CMOS design flow. In particular, the work focuses on the insertion of dummy operations, on the randomization of operands and on the generation of noise. The effectiveness and the costs of these countermeasures are analyzed. In addition, an ASIC design implementing these countermeasures is presented. The design is a strong authentication module using AES equipped with the countermeasures. First measurement results of this design based on an FPGA prototype are also part of this book. Not only researchers in the area of cryptography and security are addressed by this work but also hardware security designers.

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