MIPS architecture

MIPS architecture

Frederic P. Miller, Agnes F. Vandome, John McBrewster

     

бумажная книга



Издательство: Книга по требованию
Дата выхода: июль 2011
ISBN: 978-6-1302-0397-9
Объём: 68 страниц
Масса: 123 г
Размеры(В x Ш x Т), см: 23 x 16 x 1

MIPS is a reduced instruction set computing instruction set architecture developed by MIPS Computer Systems. The early MIPS architectures were 32-bit, and later versions were 64-bit. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 and MIPS64 . MIPS32 and MIPS64 define a control register set as well as the instruction set. Several optional extensions are also available, including MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room, and the recent addition of MIPS MT, new multithreading additions to the system similar to HyperThreading in the Intel's Pentium 4 processors. Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as Alpha.

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