A tool flow is presented for deriving accelerator circuits on an FPGA from ANSI C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based scheduling software used for spacecraft systems is explained. The goal of the tool is the derivation of a design that maximizes throughput while minimizing footprint. Results obtained are compared with a peer C to RTL tool, a space-borne embedded processor and a commodity desktop processor for a variety of problems.

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