Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. Then, two power-aware test planning approaches are proposed aiming at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected through a functional bus or using a point-to-point model. The second approach considers the systems built upon a network-on-chip (NoC) and proposes the reuse of the NoC infrastructure to test the embedded cores. This book can be useful to students, researchers, DFT practitioners, and VLSI designers that want an overview of the testing of core-based systems and that want to know the basics of the reuse of a network-on-chip as test access mechanism.

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