This book deals primarily with methods to estimate the parametric yield of a manufactured IC in the face of process variations. Various process variation models are considered including systematic and random variations. The parametric yield is defined as the probability that the IC meets its timing constraints. In the face of process variations gate delays become random variables. The problem is first formulated as an "impulse-train" approach where gate delay distributions are discretised, so as to aid the propagation of the distributions. This is a block-based approach and is seen to have limitations. Next, we consider a path- based approach where nominally critical paths as in standard static timing analysis are extracted, and the yield estimation problem is then formulated as an integral in multi-dimensional space over a feasible region. Efficient Monte-Carlo methods to solve this integral are investigated extensively. Finally the shape of the feasible region is used to propose techniques to identify those critical paths whose resizing is the key to increasing yield.

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