X2APIC

X2APIC

Lambert M. Surhone, Miriam T. Timpledon, Susan F. Marseken

     

бумажная книга



Издательство: Книга по требованию
Дата выхода: июль 2011
ISBN: 978-6-1305-8429-0
Объём: 80 страниц
Масса: 141 г
Размеры(В x Ш x Т), см: 23 x 16 x 1

High Quality Content by WIKIPEDIA articles! The x2APIC architecture provides backward compatibility to the Intel APIC Architecture/xAPIC architecture and forward extendability for future Intel platform innovations. The Intel APIC Architecture is a system of Advanced Programmable Interrupt Controllers (APICs) designed by Intel for use in Symmetric Multi-Processor (SMP) computer systems. It was originally implemented by the Intel 82093AA and 82489DX, and is found in most x86 SMP motherboards. It is one of several attempts to solve interrupt routing efficiency issues in multiprocessor computer systems. There are two components in the Intel APIC system, the Local APIC (LAPIC) and the I/O APIC. There is one LAPIC in each CPU in the system. There is typically one I/O APIC for each peripheral bus in the system.

Данное издание не является оригинальным. Книга печатается по технологии принт-он-деманд после получения заказа.

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